An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided.WFE sets the WF in the contacts as well as two Bike Parts - Brakes - Parts independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor.Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to ×10$ ) dissipation can be implemented.To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed.Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed.
The comparative simulation study shows that WFE in independent-gate SB-FinFETs can FACE WASH lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.